library verilog;
use verilog.vl_types.all;
entity dti_mux is
    generic(
        IN_WIDTH        : integer := 24;
        OUT_WIDTH       : integer := 8
    );
    port(
        data_in         : in     vl_logic_vector;
        sel             : in     vl_logic_vector;
        data_out        : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of IN_WIDTH : constant is 1;
    attribute mti_svvh_generic_type of OUT_WIDTH : constant is 1;
end dti_mux;
